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?2003 integrated device technology, inc. november 2003 dsc-5652/3 1 high-speed 2.5v 512/256/128k x 18 synchronous dual-port static ram with 3.3v or 2.5v interface preliminary idt70t3339/19/99s functional block diagram ? data input, address, byte enable and control registers ? self-timed write allows fast cycle time separate byte controls for multiplexed bus and bus matching compatibility dual cycle deselect (dcd) for pipelined output mode 2.5v (100mv) power supply for core lvttl compatible, selectable 3.3v (150mv) or 2.5v (100mv) power supply for i/os and control signals on each port industrial temperature range (-40c to +85c) is available at 166mhz and 133mhz available in a 256-pin ball grid array (bga), a 144-pin thin quad flatpack (tqfp) and 208-pin fine pitch ball grid array (fpbga) supports jtag features compliant with ieee 1149.1 due to limited pin count jtag, collision detection and interrupt are not supported on the 144-pin tqfp package features: true dual-port memory cells which allow simultaneous access of the same memory location high-speed data access ? commercial: 3.4 (200mhz)/3.6ns (166mhz)/ 4.2ns (133mhz)(max.) ? industrial: 3.6ns (166mhz)/4.2ns (133mhz) (max.) selectable pipelined or flow-through output mode counter enable and repeat features dual chip enables allow for depth expansion without additional logic interrupt and collision detection flags full synchronous operation on both ports ? 5ns cycle time, 200mhz operation (14gbps bandwidth) ? fast 3.4ns clock to data out ? 1.5ns setup to clock and 0.5ns hold on all control, data, and address inputs @ 200mhz 1. address a 18 is a nc for the idt70t3319. also, addresses a 18 and a 17 are nc's for the idt70t3399. 2. the sleep mode pin shuts off all dynamic inputs, except jtag inputs, when asserted. all static inputs, i.e., pl/ ft x and optx and the sleep mode pins themselves (zzx) are not affected during sleep mode. notes: dout0-8_l b w 0 l b w 1 l din_l oe l ub l lb l r/ w l ce 0l ce 1l ab ft /pipe l 0/1 1b 0b 1a 0a 1 0 1/0 0b 1b 0a 1a ab ft /pipe l 1/0 repeat r a 0r cnten r ads r dout0-8_r dout9-17_r i/o 0r - i/o 17r din_r addr_r oe r ub r lb r r/ w r ce 0r ce 1r ft /pipe r clk r , counter/ address reg. b w 1 r b w 0 r ft /pipe r counter/ address reg. cnten l ads l repeat l dout9-17_l i/o 0l -i/o 17l a 18l (1) a 0l addr_l 5652 drw 01 512/256/128k x 18 memory array clk l , ba 0/1 0b 1b 0a 1a 1 0 1/0 1b 0b 1a 0a a b 1/0 interrupt collision detection logic int l co l l int r col r r/ w l r/ w r ce 0 l ce1 l ce 0 r ce1 r zz control logic zz l (2) zz r (2) jtag tck trst tms tdo tdi a 18r (1)
6.42 idt70t3339/19/99s preliminary high-speed 2.5v 512/256/128k x 18 dual-port static ram industrial and commercial tempe rature ranges 2 description: the idt70t3339/19/99 is a high-speed 512/256/128k x 18 bit synchronous dual-port ram. the memory array utilizes dual-port memory cells to allow simultaneous access of any address from both ports. registers on control, data, and address inputs provide minimal setup and hold times. the timing latitude provided by this approach allows systems to be designed with very short cycle times. with an input data register, the idt70t3339/19/99 has been optimized for applications having unidirec- tional or bidirectional data flow in bursts. an automatic power down feature, controlled by ce 0 and ce 1, permits the on-chip circuitry of each port to enter a very low standby power mode. the idt70t3339/19/99 can support an operating voltage of either 3.3v or 2.5v on one or both ports, controllable by the opt pins. the power supply for the core of the device (v dd ) is at 2.5v.
6.42 idt70t3339/19/99s preliminary high-speed 2.5v 512/256/128k x 18 dual-port static ram industrial and commercial temp erature ranges 3 70t3339/19/99bc bc-256 (8) 256-pin bga top view (9) pin configuration (3,4,5,6,9) notes: 1. pin is a nc for idt70t3319 and idt70t3399. 2. pin is a nc for idt70t3399. 3. all v dd pins must be connected to 2.5v power supply. 4. all v ddq pins must be connected to appropriate power supply: 3.3v if opt pin for that port is set to v dd (2.5v), and 2.5v if opt pin for that port is set to v ss (0v). 5. all v ss pins must be connected to ground supply. 6. package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch. 7. this package code is used to reference the package diagram. 8. this text does not indicate orientation of the actual part-marking. 9. pins a15 and t15 will be v refl and v refr respectively for future hstl device. e16 i/o 7r d16 i/o 8r c16 i/o 8l b16 nc a16 nc a15 nc b15 nc c15 nc d15 nc e15 i/o 7l e14 nc d14 nc d13 v dd c12 a 6l c14 opt l b14 v dd a14 a 0l a12 a 5l b12 a 4l c11 ads l d12 v ddqr d11 v ddqr c10 clk l b11 repeat l a11 cnten l d8 v ddqr c8 nc a9 ce 1l d9 v ddql c9 lb l b9 ce 0l d10 v ddql c7 a 7l b8 ub l a8 nc b13 a 1l a13 a 2l a10 oe l d7 v ddqr b7 a 9l a7 a 8l b6 a 12l c6 a 10l d6 v ddql a5 a 14l b5 a 15l c5 a 13l d5 v ddql a4 a 17l (2) b4 a 18l (1) c4 a 16l d4 pipe/ ft l a3 nc b3 tdo c3 v ss d3 nc d2 i/o 9r c2 i/o 9l b2 nc a2 tdi a1 nc b1 int l c1 col l d1 nc e1 i/o 10r e2 i/o 10l e3 nc e4 v ddql f1 i/o 11l f2 nc f4 v ddql g1 nc g2 nc g3 i/o 12l g4 v ddqr h1 nc h2 i/o 12r h3 nc h4 v ddqr j1 i/o 13l j2 i/o 14r j3 i/o 13r j4 v ddql k1 nc k2 nc k3 i/o 14l k4 v ddql l1 i/o 15l l2 nc l3 i/o 15r l4 v ddqr m1 i/o 16r m2 i/o 16l m3 nc m4 v ddqr n1 nc n2 i/o 17r n3 nc n4 pipe/ ft r p1 col r p2 i/o 17l p3 tms p4 a 16r r1 int r r2 nc r3 trst r4 a 18r (1) t1 nc t2 tck t3 nc t4 a 17r (2) p5 a 13r r5 a 15r p12 a 6r p8 nc p9 lb r r8 ub r t8 nc p10 clk r t11 cnten r p11 ads r r12 a 4r t12 a 5r p13 a 3r p7 a 7r r13 a 1r t13 a 2r r6 a 12r t5 a 14r t14 a 0r r14 opt r p14 nc p15 nc r15 nc t15 nc t16 nc r16 nc p16 i/o 0l n16 nc n15 i/o 0r n14 nc m16 nc m15 i/o 1l m14 i/o 1r l16 i/o 2r l15 nc l14 i/o 2l k16 i/o 3l k15 nc k14 nc j16 i/o 4l j15 i/o 3r j14 i/o 4r h16 i/o 5r h15 nc h14 nc g16 nc g15 nc g14 i/o 5l f16 i/o 6l f14 i/o 6r f15 nc r9 ce 0r r11 repeat r t6 a 11r t9 ce 1r a6 a 11l b10 r/ w l c13 a 3l p6 a 10r r10 r/ w r r7 a 9r t10 oe r t7 a 8r , e5 v dd e6 v dd e7 nc e8 v ss e9 v ss e10 v ss e11 v dd e12 v dd e13 v ddqr f5 v dd f6 nc f8 v ss f9 v ss f10 v ss f12 v dd f13 v ddqr g5 v ss g6 v ss g7 v ss g8 v ss g9 v ss g10 v ss g11 v ss g12 v ss g13 v ddql h5 v ss h7 v ss h8 v ss h9 v ss h10 v ss h11 v ss h12 v ss h13 v ddql j5 zz r j6 v ss j7 v ss j8 v ss j9 v ss j10 v ss j11 v ss j12 zz l j13 v ddqr k5 v ss k6 v ss k7 v ss k8 v ss l5 v dd l6 nc l7 nc l8 v ss m5 v dd m6 v dd m7 nc m8 v ss n5 v ddqr n6 v ddqr n7 v ddql n8 v ddql k9 v ss k10 v ss k11 v ss k12 v ss l9 v ss l10 v ss l11 v ss l12 v dd m9 v ss m10 v ss m11 v dd m12 v dd n9 v ddqr n10 v ddqr n11 v ddql n12 v ddql k13 v ddqr l13 v ddql m13 v ddql n13 v dd f7 nc f11 v ss 5652 drw 02d , f3 i/o 11r 01 / 13 / 03 h6 v ss
6.42 idt70t3339/19/99s preliminary high-speed 2.5v 512/256/128k x 18 dual-port static ram industrial and commercial tempe rature ranges 4 pin configuration(con't) (3,4,5,6,9,10) notes: 3. all v dd pins must be connected to 2.5v power supply. 4. all v ddq pins must be connected to appropriate power supply: 3.3v if opt pin for that port is set to v dd (2.5v), and 2.5v if opt pin for that port is set to v ss (0v). 5. all v ss pins must be connected to ground supply. 6. package body is approximately 20mm x 20mm x 1.4mm. 7. this package code is used to reference the package diagram. 8. this text does not indicate orientation of the actual part-marking. 9. due to limited pin count, jtag, collison detection and interrupt are not supported in the dd-144 package. 10. pins 109 and 72 will be v refl and v refr respectively for future hstl device. 1. pin is a nc for idt70t3319 and idt70t3399. 2. pin is a nc for idt70t3399. v ss v ddqr v ss i/o 9l i/o 9r i/o 10l i/o 10r i/o 11l i/o 11r v ddql v ss i/o 12l i/o 12r v ddqr zz r v dd v dd v ss v ss v ddql v ss i/o 13r i/o 13l i/o 14r i/o 14l v ddqr v ss i/o 15r i/o 15l i/o 16r i/o 16l i/o 17r i/o 17l v ss v ddql nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 1 4 4 1 4 3 1 4 2 1 4 1 1 4 0 1 3 9 1 3 8 1 3 7 1 3 6 1 3 5 1 3 4 1 3 3 1 3 2 1 3 1 1 3 0 1 2 9 1 2 8 1 2 7 1 2 6 1 2 5 1 2 4 1 2 3 1 2 2 1 2 1 1 2 0 1 1 9 1 1 8 1 1 7 1 1 6 1 1 5 1 1 4 1 1 3 1 1 2 1 1 1 1 1 0 1 0 9 p l / f t r n c n c a 1 8 r ( 1 ) a 1 7 r ( 2 ) a 1 6 r a 1 5 r a 1 4 r a 1 3 r a 1 2 r a 1 1 r a 1 0 r a 9 r a 8 r a 7 r u b r l b r c e 1 r c e 0 r v d d v s s c l k r o e r r / w r a d s r c n t e n r r e p e a t r a 6 r a 5 r a 4 r a 3 r a 2 r a 1 r a 0 r v d d n c opt l v ddqr v ss i/o 8l i/o 8r i/o 7l i/o 7r i/o 6l i/o 6r v ss v ddql i/o 5l i/o 5r v ss v ddqr v dd v dd v ss v ss zz l v ddql i/o 4r i/o 4l i/o 3r i/o 3l v ss v ddqr i/o 2r i/o 2l i/o 1r i/o 1l i/o 0r i/o 0l v ss v ddql opt r p l / f t l n c n c a 1 8 l ( 1 ) a 1 7 l ( 2 ) a 1 6 l a 1 5 l a 1 4 l a 1 3 l a 1 2 l a 1 1 l a 1 0 l a 9 l a 8 l a 7 l u b l l b l c e 1 l c e 0 l v d d v s s c l k l o e l r / w l a d s l c n t e n l r e p e a t l a 6 l a 5 l a 4 l a 3 l a 2 l a 1 l a 0 l v d d n c 70t3339/19/99dd dd-144 (7) 144-pin tqfp top view (8) 5652 drw 02a , 01/07/03
6.42 idt70t3339/19/99s preliminary high-speed 2.5v 512/256/128k x 18 dual-port static ram industrial and commercial temp erature ranges 5 pin configurations(con't) (3,4,5,6,9) 17 16 15 14 12 13 10 9 8 7 6 5 4 3 2 1 11 a b c d e f g h j k l m n p r t u i/o 9l int l v ss tdo a 2l a 4l clk l a 8l a 12l a 16l nc opt l nc v ss col l tdi a 1l a 5l a 9l a 13l a 17l (2) v ddql i/o 9r v ddqr pipe/ ft l a 3l a 6l nc a 10l a 14l a 18l (1) nc nc v ss i/o 10l nc nc i/o 11l nc v ddqr i/o 10 r nc i/o 11r nc v ss v dd nc i/o 12l v dd v ss nc v ss i/o 12r repeat r nc i/o 14l v ddqr v ddql i/o 15r nc v ss nc nc a 15l a 11l a 7l a 0l nc i/o 7l nc i/o 6l i/o 8r ub l nc i/o 8l v ddql ce 0l ce 1l lb l repeat l oe l i/o 0l i/o 2l i/o 1r ads r r/ w r nc i/o 16r i/o 15 l trst a 13 r a 12r nc v dd clk r i/o 0r nc nc nc nc a 17r (2) tck tms a 5r a 9r ce 0r ce 1r v dd v ss nc nc nc a 16r nc a 18r (1) a 14r a 10 r ub r v ss v ddql i/o 1l i/o 2r nc int r nc a 15r a 11r a 7r lb r oe r v ss nc v ddql opt r nc 70t3339/19/99bf bf-208 (7) 208-pin fpbga top view (8) 5652 drw 02c i/o 14r v ddql v ss v ddqr nc col r nc nc i/o 7r nc r/ w l nc ads l v ddql i/o 13r cnten l zz r i/o 13l v ss i/o 16l v ddqr v ss i/o 17r i/o 17l v ddql v ss pipe/ ft r a 8r cnten r a 6r a 3r a 1r a 2r a 0r i/o 3l i/o 4l a 4r v dd v ss v ss v ddqr v ddql v ss v ddqr v ss i/o 3r i/o 4r v ss v ddqr v ss v dd v dd v ss i/o 5r i/o 5l v ddqr i/o 6r v ss v ss v ddql v dd v ss v ddqr v ss v dd v dd v ss v dd v ss nc zz l nc v ss 01/13/03 notes: 3. all v dd pins must be connected to 2.5v power supply. 4. all v ddq pins must be connected to appropriate power supply: 3.3v if opt pin for that port is set to v dd (2.5v), and 2.5v if opt pin for that port is set to v ss (0v). 5. all v ss pins must be connected to ground supply. 6. package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch. 7. this package code is used to reference the package diagram. 8. this text does not indicate orientation of the actual part-marking. 9. pins b14 and r14 will be v refl and v refr respectively for future hstl device. 1. pin is a nc for idt70t3319 and idt70t3399. 2. pin is a nc for idt70t3399.
6.42 idt70t3339/19/99s preliminary high-speed 2.5v 512/256/128k x 18 dual-port static ram industrial and commercial tempe rature ranges 6 pin names notes: 1. v dd , opt x , and v ddqx must be set to appropriate operating levels prior to applying inputs on the i/os and controls for that port. 2. opt x selects the operating voltage levels for the i/os and controls on that port. if opt x is set to v dd (2.5v), then that port's i/os and controls will operate at 3.3v levels and v ddqx must be supplied at 3.3v. if opt x is set to v ss (0v), then that port's i/os and address controls will operate at 2.5v levels and v ddqx must be supplied at 2.5v. the opt pins are independent of one another?both ports can operate at 3.3v levels, both can operate at 2.5v levels, or either can operate at 3.3v with the other at 2.5v. 3. when repeat x is asserted, the counter will reset to the last valid address loaded via ads x . 4. the sleep mode pin shuts off all dynamic inputs, except jtag inputs, when asserted. all static inputs, i.e., pl/ ft x and optx and the sleep mode pins themselves (zzx) are not affected during sleep mode. 5. due to limited pin count, jtag, collision detection and interrupt are not supported in the dd-144 package. 6. address a 18x is a nc for the idt70t3319. also, addresses a 18x and a 17x are nc's for the idt70t3399. 7. chip enables and byte enables are double buffered when pl/ ft = v ih , i.e., the signals take two cycles to deselect. left port right port names ce 0l , ce 1l ce 0r , ce 1r chip enables (input) (7) r/ w l r/ w r read/write enable (input) oe l oe r output enable (input) a 0l - a 18l (6) a 0r - a 18r (6) address (input) i/o 0l - i/o 17l i/o 0r - i/o 17r data input/output clk l clk r clock (input) pl/ ft l pl/ ft r pipeline/flow-through (input) ads l ads r address strobe enable (input) cnten l cnten r counter enable (input) repeat l repeat r counter repeat (3) ub l ub r upper byte enable (i/o 9 - i/o 17 ) (7) lb l lb r lower byte enable (i/o 0 - i/o 8 ) (7) v ddql v ddqr power (i/o bus) (3.3v or 2.5v) (1) (input ) opt l opt r option for selecting v ddqx (1,2) (input) zz l zz r sleep mode pin (4) (input) v dd power (2.5v) (1) (input) v ss ground (0v) (input) tdi (5) test data input tdo (5) test data output tck (5) test logic clock (10mhz) (input) tms (5) test mode select (input) trst (5) reset (initialize tap controller) (input) int l (5) int r (5) interrupt flag (output) col l (5) col r (5) collision alert (output) 5652 tbl 01
6.42 idt70t3339/19/99s preliminary high-speed 2.5v 512/256/128k x 18 dual-port static ram industrial and commercial temp erature ranges 7 notes: 1. "h" = v ih, "l" = v il, "x" = don't care. 2. ads , cnten , repeat = v ih . 3. oe and zz are asynchronous input signals. 4. it is possible to read or write any combination of bytes during a given access. a few representative samples have been illust rated here. truth table iread/write and enable control (1,2,3,4) truth table iiaddress counter control (1,2) notes: 1. "h" = v ih, "l" = v il, "x" = don't care. 2. read and write operations are controlled by the appropriate setting of r/ w , ce 0 , ce 1 , ub , lb and oe . 3. outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle. 4. ads and repeat are independent of all other memory control signals including ce 0 , ce 1 , ub and lb . 5. the address counter advances if cnten = v il on the rising edge of clk, regardless of all other memory control signals including ce 0 , ce 1 , ub and lb . 6. when repeat is asserted, the counter will reset to the last valid address loaded via ads . this value is not set at power-up: a known location should be loaded via ads during initialization if desired. any subsequent ads access during operations will update the repeat address location. oe clk ce 0 ce 1 ub lb r/ w zz upper byte i/o 9-17 lower byte i/o 0-8 mode x h x x x x l high-z high-z deselected?power down x x l x x x l high-z high-z deselected?power down x l h h h x l high-z high-z both bytes deselected x lhhlll high-z d in write to lower byte only x lhlhll d in high-z write to upper byte only x lhllll d in d in write to both bytes l lhhlhl high-z d out read lower byte only l lhlhhl d out high-z read upper byte only l lhllhl d out d out read bo th byte s h l h l l x l high-z high-z outputs disabled x x x x x x x h high-z high-z sleep mode 5652 tbl 02 address previous internal address internal address used clk ads cnten repeat (6) i/o (3) mode an x an l (4) xhd i/o (n) external address used xanan + 1 h l (5) hd i/o (n+1) counter enabled?internal address generation x an + 1 an + 1 hh hd i/o (n+1) external address blocked?counter disabled (an + 1 reused) xxan xx l (4) d i/o (n) counter set to last valid ads load 5652 tbl 03
6.42 idt70t3339/19/99s preliminary high-speed 2.5v 512/256/128k x 18 dual-port static ram industrial and commercial tempe rature ranges 8 recommended dc operating conditions with v ddq at 3.3v symbol parameter min. typ. max. unit v dd core supply voltage 2.4 2.5 2.6 v v ddq i/o supply voltage (3) 3.15 3.3 3.45 v v ss ground 0 0 0 v v ih input high voltage (address, control &data i/o inputs) (3) 2.0 ____ v ddq + 150mv (2) v v ih input high voltage _ jtag 1.7 ____ v dd + 100mv (2) v v ih input high voltage - zz, opt, pipe/ ft v dd - 0.2v ____ v dd + 100mv (2) v v il input low voltage -0.3 (1) ____ 0.8 v v il input low voltage - zz, opt, pipe/ ft -0.3 (1) ____ 0.2 v 5652 tbl 05b notes: 1. v il (min.) = -1.0v for pulse width less than t cyc /2, or 5ns, whichever is less. 2. v ih (max.) = v ddq + 1.0v for pulse width less than t cyc /2 or 5ns, whichever is less. 3. to select operation at 3.3v levels on the i/os and controls of a given port, the opt pin for that port must be set to v dd (2.5v), and v ddqx for that port must be supplied as indicated above. recommended dc operating conditions with v ddq at 2.5v symbol parameter min. typ. max. unit v dd core supply voltage 2.4 2.5 2.6 v v ddq i/o supply voltage (3) 2.4 2.5 2.6 v v ss ground 0 0 0 v v ih input high volltage (address, control & data i/o inputs) (3) 1.7 ____ v ddq + 100mv (2) v v ih input high voltage _ jtag 1.7 ____ v dd + 100mv (2) v v ih input high voltage - zz, opt, pipe/ ft v dd - 0.2v ____ v dd + 100mv (2) v v il input low voltage -0.3 (1) ____ 0.7 v v il input low voltage - zz, opt, pipe/ ft -0.3 (1) ____ 0.2 v 5652 tbl 05a notes: 1. v il (min.) = -1.0v for pulse width less than t cyc /2 or 5ns, whichever is less. 2. v ih (max.) = v ddq + 1.0v for pulse width less than t cyc /2 or 5ns, whichever is less. 3. to select operation at 2.5v levels on the i/os and controls of a given port, the opt pin for that port must be set to v ss (0v), and v ddqx for that port must be supplied as indicated above. maximum operating temperature and supply voltage (1) grade ambient temperature gnd v dd commercial 0 o c to +70 o c0v2.5v + 100mv industrial -40 o c to +85 o c0v2.5v + 100mv 5652 tbl 04 notes: 1. this is the parameter ta. this is the "instant on" case temperature.
6.42 idt70t3339/19/99s preliminary high-speed 2.5v 512/256/128k x 18 dual-port static ram industrial and commercial temp erature ranges 9 absolute maximum ratings (1) symbol rating commercial & industrial unit v term (v dd ) v dd terminal voltage with respe ct to gnd -0.5 to 3.6 v v term (2) (v ddq ) v ddq terminal voltage with respe ct to gnd -0.3 to v ddq + 0.3 v v term (2) (inputs and i/o' s) input and i/o terminal voltage with re sp ect to gnd -0.3 to v ddq + 0.3 v t bias (3) temperature under bias -55 to +125 o c t stg storage temperature -65 to +150 o c t jn junction temperature +150 o c i out (for v ddq = 3.3v) dc output current 50 ma i out (for v ddq = 2.5v) dc output current 40 ma 5652 tbl 06 notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. this is a steady-state dc parameter that applies after the power supply has reached its nominal operating value. power sequencing is not necessary; however, the voltage on any input or i/o pin cannot exceed v ddq during power supply ramp up. 3. ambient temperature under dc bias. no ac conditions. chip deselected. dc electrical characteristics over the operating temperature and supply voltage range (v dd = 2.5v 100mv) symbol parameter test conditions 70t3339/19/99s unit min. max. |i li | input leakage current (1) v ddq = max., v in = 0v to v ddq ___ 10 a |i li | jtag & zz input leakage current (1,2) v dd = max. , v in = 0v to v dd ___ 30 a |i lo | output leakage current (1,3) ce 0 = v ih or ce 1 = v il , v out = 0v to v ddq ___ 10 a v ol (3.3v) output low voltage (1) i ol = +4ma, v ddq = min. ___ 0.4 v v oh (3.3v) output high voltage (1) i oh = -4ma, v ddq = min. 2.4 ___ v v ol (2.5v) output low voltage (1) i ol = +2ma, v ddq = min. ___ 0.4 v v oh (2.5v) output high voltage (1) i oh = -2ma, v ddq = min. 2.0 ___ v 5652 tbl 08 notes: 1. v ddq is selectable (3.3v/2.5v) via opt pins. refer to p.6 for details. 2. applicable only for tms, tdi and trst inputs. 3. outputs tested in tri-state mode. capacitance (1) (t a = +25c, f = 1.0mhz) pqfp only symbol parameter conditions (2) max. unit c in input capacitanc e v in = 3dv 8 pf c out (3) output capacitance v out = 3dv 10.5 pf 5652 tbl 07 notes: 1. these parameters are determined by device characterization, but are not production tested. 2. 3dv references the interpolated capacitance when the input and output switch from 0v to 3v or from 3v to 0v. 3. c out also references c i/o .
6.42 idt70t3339/19/99s preliminary high-speed 2.5v 512/256/128k x 18 dual-port static ram industrial and commercial tempe rature ranges 10 dc electrical characteristics over the operating temperature and supply voltage range (3) (v dd = 2.5v 100mv) 70t3339/19/99 s200 com'l only (8) 70t3339/19/99 s166 com'l & ind (7) 70t3339/19/99 s133 com'l & ind symbol parameter test condition version typ. (4) max. typ. (4) max. typ. (4) max. unit i dd dynamic operating current (both ports active) ce l and ce r = v il , outputs disabled, f = f max (1) com'l s 375 525 320 450 260 370 ma ind s ___ ___ 320 510 260 450 i sb1 (6) standby current (both ports - ttl level inputs) ce l = ce r = v ih f = f max (1) com'l s 205 270 175 230 140 190 ma ind s ___ ___ 175 275 140 235 i sb2 (6) standby current (one port - ttl level inputs) ce "a" = v il and ce "b" = v ih (5) active port outputs disabled, f=f max (1) com'l s 300 375 250 325 200 250 ma ind s ___ ___ 250 365 200 310 i sb3 full standby current (both ports - cmos level inputs) both ports ce l and ce r > v ddq - 0.2v, v in > v ddq - 0.2v or v in < 0.2v, f = 0 (2) com'l s 5 15 5 15 5 15 ma ind s ___ ___ 520520 i sb4 (6) full standby current (one port - cmos level inputs) ce "a" < 0.2v and ce "b" > v ddq - 0.2v (5) v in > v ddq - 0.2v or v in < 0.2v active port, outputs disabled, f = f max (1) com'l s 300 375 250 325 200 250 ma ind s ___ ___ 250 365 200 310 izz sleep mode current (both ports - ttl level inputs) zz l = zz r = v ih f=f max (1) com'l s 5 15 5 15 5 15 ma ind s ___ ___ 520520 5652 tbl 09 notes: 1. at f = f max , address and control lines (except output enable) are cycling at the maximum frequency clock cycle of 1/t cyc , using "ac test conditions". 2. f = 0 means no address, clock, or control lines change. applies only to input at cmos level standby. 3. port "a" may be either left or right port. port "b" is the opposite from port "a". 4. v dd = 2.5v, t a = 25c for typ, and are not production tested. i dd dc (f=0) = 15ma (typ). 5. ce x = v il means ce 0x = v il and ce 1x = v ih ce x = v ih means ce 0x = v ih or ce 1x = v il ce x < 0.2v means ce 0x < 0.2v and ce 1x > v dd - 0.2v ce x > v dd - 0.2v means ce 0x > v dd - 0.2v or ce 1x - 0.2v "x" represents "l" for left port or "r" for right port. 6. i sb 1 , i sb 2 and i sb 4 will all reach full standby levels (i sb 3 ) on the appropriate port(s) if zz l and/or zz r = v ih . 7. 166mhz i-temp is not available in the bf-208 package. 8. 200mhz is not available in the bf-208 and dd-144 packages.
6.42 idt70t3339/19/99s preliminary high-speed 2.5v 512/256/128k x 18 dual-port static ram industrial and commercial temp erature ranges 11 input pulse levels (address & controls) input pulse le ve ls (i/os) input ris e/fall times input timing reference levels output reference levels output load gnd to 3 . 0v/gnd to 2.4v gnd to 3.0v/gnd to 2.4v 2ns 1.5v/1.25v 1.5v/1.25v figures 1 and 2 5652 tbl 10 ac test conditions (v ddq - 3.3v/2.5v) figure 1. ac output test load. 1.5v/1.25 50 ? 50 ? ? capacitance (pf) from ac test load 5652 drw 04 ? tcd (typical, ns)
6.42 idt70t3339/19/99s preliminary high-speed 2.5v 512/256/128k x 18 dual-port static ram industrial and commercial tempe rature ranges 12 ac electrical characteristics over the operating temperature range (read and write cycle timing) (2,3) (v dd = 2.5v 100mv, t a = 0c to +70c) notes: 1. the pipelined output parameters (t cyc2 , t cd2 ) apply to either or both left and right ports when ft /pipe x = v dd (2.5v). flow-through parameters (t cyc1 , t cd1 ) apply when ft /pipe = v ss (0v) for that port. 2. all input signals are synchronous with respect to the clock except for the asynchronous output enable ( oe ), ft /pipe and opt. ft /pipe and opt should be treated as dc signals, i.e. steady state during operation. 3. these values are valid for either level of v ddq (3.3v/2.5v). see page 6 for details on selecting the desired operating voltage levels for each port. 4. 166mhz i-temp is not available in the bf-208 package. 5. 200mhz is not available in the bf-208 and dd-144 packages. 6. guaranteed by design (not production tested). 70t3339/19/99 s200 com'l only (5) 70t3339/19/99 s166 com'l & ind (4) 70t3339/19/99 s133 com'l & ind symbol parameter min.max.min.max.min.max.unit t cyc1 clock cycle time (flow-through) (1) 15 ____ 20 ____ 25 ____ ns t cyc2 clock cycle time (pipelined) (1) 5 ____ 6 ____ 7.5 ____ ns t ch1 clock high time (flow-through) (1) 6 ____ 8 ____ 10 ____ ns t cl1 clock low time (flow-through) (1) 6 ____ 8 ____ 10 ____ ns t ch2 clock high time (pipelined) (2) 2 ____ 2.4 ____ 3 ____ ns t cl2 clock low time (pipelined) (1) 2 ____ 2.4 ____ 3 ____ ns t sa address setup time 1.5 ____ 1.7 ____ 1.8 ____ ns t ha address hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t sc chip enable setup time 1.5 ____ 1.7 ____ 1.8 ____ ns t hc chip enable hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t sb byte enable setup time 1.5 ____ 1.7 ____ 1.8 ____ ns t hb byte enable hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t sw r/w setup time 1.5 ____ 1.7 ____ 1.8 ____ ns t hw r/w hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t sd input data setup time 1.5 ____ 1.7 ____ 1.8 ____ ns t hd input data hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t sad ads setup time 1.5 ____ 1.7 ____ 1.8 ____ ns t had ads hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t scn cnten setup time 1.5 ____ 1.7 ____ 1.8 ____ ns t hcn cnten hold time 0.5 ____ 0.5 ____ 0.5 ____ ns t srpt repeat setup time 1.5 ____ 1.7 ____ 1.8 ____ ns t hrpt repeat ho ld time 0.5 ____ 0.5 ____ 0.5 ____ ns t oe output enable to data valid ____ 4.4 ____ 4.4 ____ 4.6 ns t olz (6) output enable to output low-z 1 ____ 1 ____ 1 ____ ns t ohz (6) output enable to output high-z 1 3.4 1 3.6 1 4.2 ns t cd1 clock to data valid (flow-through) (1) ____ 10 ____ 12 ____ 15 ns t cd2 clock to data valid (pipelined) (1) ____ 3.4 ____ 3.6 ____ 4.2 ns t dc data output hold after clock high 1 ____ 1 ____ 1 ____ ns t ckhz (6) clock high to output high-z 1 3.4 1 3.6 1 4.2 ns t cklz (6) clock high to output low-z 1 ____ 1 ____ 1 ____ ns t ins interrupt flag set time ____ 7 ____ 7 ____ 7ns t inr interrupt flag reset time ____ 7 ____ 7 ____ 7ns t cols collision flag set time ____ 3.4 ____ 3.6 ____ 4.2 ns t colr collision flag reset time ____ 3.4 ____ 3.6 ____ 4.2 ns t zzsc sleep mode set cycles 2 ____ 2 ____ 2 ____ cycles t zzrc sleep mode recovery cycles 3 ____ 3 ____ 3 ____ cycles port-to-port delay t co clock-to-clock offset 4 ____ 5 ____ 6 ____ ns t ofs clock-to-clock offset for collision detection please refer to collision detection timing table on page 21 5652 tbl 11
6.42 idt70t3339/19/99s preliminary high-speed 2.5v 512/256/128k x 18 dual-port static ram industrial and commercial temp erature ranges 13 timing waveform of read cycle for pipelined operation ( ft /pipe 'x' = v ih ) (2) timing waveform of read cycle for flow-through output ( ft /pipe "x" = v il ) (2,6) notes: 1. oe is asynchronously controlled; all other inputs depicted in the above waveforms are synchronous to the rising clock edge. 2. ads = v il , cnten and repeat = v ih . 3. the output is disabled (high-impedance state) by ce 0 = v ih , ce 1 = v il , ub , lb = v ih following the next rising edge of the clock. refer to truth table 1. 4. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 5. if ub , lb was high, then the appropriate byte of data out for qn + 2 would be disabled (high-impedance state). 6. "x" denotes left or right port. the diagram is with respect to that port. an an + 1 an + 2 an + 3 t cyc2 t ch2 t cl2 r/ w address ce 0 clk ce 1 ub , lb (3) data out oe t cd2 t cklz qn qn + 1 qn + 2 t ohz t olz t oe 5652 drw 05 (1) (1) t sc t hc t sb t hb t sw t hw t sa t ha t dc t sc t hc t sb t hb (4) (1 latency) (5) (5) , an an + 1 an + 2 an + 3 t cyc1 t ch1 t cl1 r/ w address data out ce 0 clk oe t sc t hc t cd1 t cklz qn qn + 1 qn + 2 t ohz t olz t oe t ckhz 5652 drw 06 (5) (1) ce 1 ub , lb (3) t sb t hb t sw t hw t sa t ha t dc t dc (4) t sc t hc t sb t hb ,
6.42 idt70t3339/19/99s preliminary high-speed 2.5v 512/256/128k x 18 dual-port static ram industrial and commercial tempe rature ranges 14 timing waveform of a multi-device pipelined read (1,2) notes: 1. b1 represents device #1; b2 represents device #2. each device consists of one idt70t3339/19/99 for this waveform, and are setup for depth expansion in this example. address (b1) = address (b2) in this situation. 2. ub , lb , oe , and ads = v il ; ce 1(b1) , ce 1(b2) , r/ w , cnten , and repeat = v ih . timing waveform of a multi-device flow-through read (1,2) , t sc t hc ce 0(b1) address (b1) a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha clk q 0 q 1 q 3 data out(b1) t ch2 t cl2 t cyc2 address (b2) a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha ce 0(b2) data out(b2) q 2 q 4 t cd2 t cd2 t ckhz t cd2 t cklz t dc t ckhz t cd2 t cklz t sc t hc t ckhz t cklz t cd2 a 6 a 6 t dc t sc t hc t sc t hc 5652 drw 07 t sc t hc ce 0(b1) address (b1) a 0 a 1 a 2 a 3 a 4 a 5 t sa t h a clk 5652 drw 08 d 0 d 3 t cd1 t cklz t ckhz (1) (1) d 1 data out(b1) t ch1 t cl1 t cyc1 (1) address (b2) a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha ce 0(b2) data out(b2) d 2 d 4 t cd1 t cd1 t ckhz t dc t cd1 t cklz t sc t hc (1) t ckhz (1) t cklz (1) t cd1 a 6 a 6 t dc t sc t hc t sc t hc d 5 t cd1 t cklz (1) t ckhz (1) ,
6.42 idt70t3339/19/99s preliminary high-speed 2.5v 512/256/128k x 18 dual-port static ram industrial and commercial temp erature ranges 15 timing waveform of left port write to pipelined right port read (1,2,4) timing waveform with port-to-port flow-through read (1,2,4) notes: 1. ce 0 , ub , lb , and ads = v il ; ce 1 , cnten , and repeat = v ih . 2. oe = v il for the right port, which is being read from. oe = v ih for the left port, which is being written to. 3. if t co < minimum specified, then data from port "b" read is not valid until following port "b" clock cycle (i.e., time from write to v alid read on opposite port will be t co + t cyc + t cd1 ). if t co > minimum, then data from port "b" read is available on first port "b" clock cycle (i.e., time from write to valid read on oppo site port will be t co + t cd1 ). 4. all timing is the same for both left and right ports. port "a" may be either left or right port. port "b" is the opposite of port "a". clk "a" r/ w "a " address "a" data in"a" clk "b" r/ w "b" address "b" data out"b" t sw t hw t sa t ha t sd t hd t sw t hw t sa t ha t co (3 ) t cd2 no match valid no matc h matc h matc h valid 5652 drw 09 t dc , data in "a" clk "b" r/ w "b" address "a" r/ w "a" clk "a" address "b" no match match no match match valid t cd1 t dc data out "b" 5652 drw 10 valid valid t sw t hw t sa t ha t sd t hd t hw t cd1 t co t dc t sa t sw t ha (3) , notes: 1. ce 0 , ub , lb , and ads = v il ; ce 1 , cnten , and repeat = v ih . 2. oe = v il for port "b", which is being read from. oe = v ih for port "a", which is being written to. 3. if t co < minimum specified, then data from port "b" read is not valid until following port "b" clock cycle (ie, time from write to val id read on opposite port will be t co + 2 t cyc2 + t cd2 ). if t co > minimum, then data from port "b" read is available on first port "b" clock cycle (ie, time from write to valid read on oppos ite port will be t co + t cyc2 + t cd2 ). 4. all timing is the same for left and right ports. port "a" may be either left or right port. port "b" is the opposite of port "a"
6.42 idt70t3339/19/99s preliminary high-speed 2.5v 512/256/128k x 18 dual-port static ram industrial and commercial tempe rature ranges 16 timing waveform of pipelined read-to-write-to-read ( oe = v il ) (2) timing waveform of pipelined read-to-write-to-read ( oe controlled) (2) notes: 1. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 2. ce 0 , ub , lb , and ads = v il ; ce 1 , cnten , and repeat = v ih . 3. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 4. this timing does not meet requirements for fastest speed grade. this waveform indicates how logically it could be done if tim ing so allows. r/ w address an an +1 an + 2 an + 2 an + 3 an + 4 data in dn + 2 ce 0 clk 5652 drw 11 qn qn + 3 data out ce 1 ub , lb t cd2 t ckhz t cklz t cd2 t sc t hc t sb t hb t sw t hw t sa t ha t ch2 t cl2 t cyc2 read nop read t sd t hd (3) (1) t sw t hw write (4) , r/ w address an an +1 an + 2 an + 3 an + 4 an + 5 data in dn + 3 dn + 2 ce 0 clk 5652 drw 12 data out qn qn + 4 ce 1 ub , lb oe t ch2 t cl2 t cyc2 t cklz t cd2 t ohz t cd2 t sd t hd read write read t sc t hc t sb t hb t sw t hw t sa t ha (3) (1) t sw t hw (4) , notes: 1. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 2. ce 0 , ub , lb , and ads = v il ; ce 1 , cnten , and repeat = v ih . "nop" is "no operation". 3. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 4. "nop" is "no operation." data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42 idt70t3339/19/99s preliminary high-speed 2.5v 512/256/128k x 18 dual-port static ram industrial and commercial temp erature ranges 17 timing waveform of flow-through read-to-write-to-read ( oe = v il ) (2) timing waveform of flow-through read-to-write-to-read ( oe controlled) (2) notes: 1. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 2. ce 0 , ub , lb , and ads = v il ; ce 1 , cnten , and repeat = v ih . 3. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 4. "nop" is "no operation." data in memory at the selected address may be corrupted and should be re-written to guarantee data i ntegrity. r/ w address an an +1 an + 2 an + 2 an + 3 an + 4 data in dn + 2 ce 0 clk 5652 drw 13 qn data out ce 1 ub , lb t cd1 qn + 1 t ch1 t cl1 t cyc1 t sd t hd t cd1 t cd1 t dc t ckhz qn + 3 t cd1 t dc t sc t hc t sb t hb t sw t hw t sa t ha read nop read t cklz (3) (1) t sw t hw write (4) , r/ w address an an +1 an + 2 an + 3 an + 4 an + 5 (3) data in dn + 2 ce 0 clk 5652 drw 14 qn data out ce 1 ub , lb t cd1 t ch1 t cl1 t cyc1 t sd t hd t cd1 t dc qn + 4 t cd1 t dc t sc t hc t sb t hb t sw t hw t sa t ha read write read t cklz (1) dn + 3 t ohz t sw t hw oe t oe ,
6.42 idt70t3339/19/99s preliminary high-speed 2.5v 512/256/128k x 18 dual-port static ram industrial and commercial tempe rature ranges 18 timing waveform of pipelined read with address counter advance (1) address an clk data out qx - 1 (2) qx qn qn + 2 (2) qn + 3 ads cnten t cyc2 t ch2 t cl2 5652 drw 15 t sa t ha t sad t had t cd2 t dc read external address read with counter counter hold t sad t had t scn t hcn read with counter qn + 1 , notes: 1. ce 0 , oe , ub , lb = v il ; ce 1 , r/ w , and repeat = v ih . 2. if there is no address change via ads = v il (loading a new address) or cnten = v il (advancing the address), i.e. ads = v ih and cnten = v ih , then the data output remains constant for subsequent clocks. timing waveform of flow-through read with address counter advance (1) address an clk data out qx (2) qn qn + 1 qn + 2 qn + 3 (2) qn + 4 ads cnten t cyc1 t ch1 t cl1 5652 drw 16 t sa t ha t sad t had read external address read with counter counter hold t cd1 t dc t sad t had t scn t hcn read with counter ,
6.42 idt70t3339/19/99s preliminary high-speed 2.5v 512/256/128k x 18 dual-port static ram industrial and commercial temp erature ranges 19 timing waveform of write with address counter advance (flow-through or pipelined inputs) (1) timing waveform of counter repeat (2) notes: 1. ce 0 , ub , lb , and r/ w = v il ; ce 1 and repeat = v ih . 2. ce 0 , ub , lb = v il ; ce 1 = v ih . 3. the "internal address" is equal to the "external address" when ads = v il and equals the counter output when ads = v ih . 4. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 5. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 6. no dead cycle exists during repeat operation. a read or write cycle may be coincidental with the counter repeat cycle: address loaded by last valid ads load will be accessed. extra cycles are shown here simply for clarification. for more information on repeat function refer to truth table ii. 7. cnten = v il advances internal address from ?an? to ?an +1?. the transition shown indicates the time required for the counter to advance. t he ?an +1?address is written to during this cycle. address an clk data in dn dn + 1 dn + 1 dn + 2 ads cnten t ch2 t cl2 t cyc2 5652 drw 17 internal (3) address an (7) an + 1 an + 2 an + 3 an + 4 dn + 3 dn + 4 t sa t ha t sad t had write counter hold write with counter write external address write with counter t sd t hd t scn t hc n , address an d 0 t ch2 t cl2 t cyc2 q last q last+1 last ads load clk data in r/ w repeat 5652 drw 18 internal (3) address ads cnten t srpt t hrpt t sd t hd t sw t hw execute repeat write last ads address read last ads address read last ads address + 1 read address n qn an + 1 an + 2 read address n+1 data out t sa t ha last ads +1 an an + 1 (4) (5) (6) ax t sad t had t scn t hcn ,
6.42 idt70t3339/19/99s preliminary high-speed 2.5v 512/256/128k x 18 dual-port static ram industrial and commercial tempe rature ranges 20 waveform of interrupt timing (2) notes: 1. ce 0 = v il and ce 1 = v ih 2. all timing is the same for left and right ports. 3. address is for internal register, not the external bus, i.e., address needs to be qualified by one of the address counter con trol signals. t sw t hw 7ffff clk r ce r (1) address r (3) t sa t ha 7ffff t sc t hc t inr clk l r/ w l address l (3) ce l (1) t sa t ha t sc t hc 5652 drw 19 int r t ins r/ w r t sw t hw truth table iii interrupt flag (1) left port right port function clk l r/ w l (2) ce l (2) a 18l -a 0l (3,4,5) int l clk r r/ w r (2) ce r (2) a 18r -a 0r (3,4,5) int r l l 7ffff x xx x lset right int r flag xx x x h l 7ffff h reset right int r flag xx x l l l 7fffe x set left int l flag h l 7fffe h x x x x reset left int l flag 5652 tbl 12 notes: 1. int l and int r must be initialized at power-up by resetting the flags. 2. ce 0 = v il and ce 1 = v ih . r/ w and ce are synchronous with respect to the clock and need valid set-up and hold times. 3. a18 x is a nc for idt70t3319, therefore interrupt addresses are 3ffff and 3fffe. 4. a18 x and a17 x are nc's for idt70t3399, therefore interrupt addresses are 1ffff and 1fffe. 5. address is for internal register, not the external bus, i.e., address needs to be qualified by one of the address counter con trol signals.
6.42 idt70t3339/19/99s preliminary high-speed 2.5v 512/256/128k x 18 dual-port static ram industrial and commercial temp erature ranges 21 t sa t ha (3) t cols t colr a 3 ha t sa t t cols t colr 5652 drw 20 col r col l (4) clk r address r a 0 a 1 a 2 t ofs (4) clk l address l a 0 a 1 a 2 a 3 t ofs waveform of collision timing (1,2) both ports writing with left port clock leading collision detection timing (3,4) cycle time t ofs (ns) region 1 (ns) (1) region 2 (ns) (2) 5ns 0 - 2.8 2.81 - 4.6 6ns 0 - 3.8 3.81 - 5.6 7.5ns 0 - 5.3 5.31 - 7.1 5652 tbl 13 notes: 1. region 1 both ports show collision after 2nd cycle for addresses 0, 2, 4 etc. 2. region 2 leading port shows collision after 3rd cycle for addresses 0, 3, 6, etc. while trailing port shows collision after 2nd cycle for addresses 0, 2, 4 etc. 3. all the production units are tested to midpoint of each region. 4. these ranges are based on characterization of a typical device. left port right port function clk l r/ w l (1) ce l (1) a 18l -a 0l (2) col l clk r r/ w r (1) ce r (1) a 18r -a 0r (2) col r hlmatchh hlmatchh both ports reading. not a valid collision. no flag output on either port. hlmatchl llmatchh left port reading, right port writing. valid collision, flag output on left port. llmatchh hlmatchl right port reading, left port writing. valid collision, flag output on right port. llmatchl llmatchl both ports writing. valid collision. flag output on both ports. 5652 tbl 14 truth table iv collision detection flag notes: 1. ce 0 = v il and ce 1 = v ih . r/ w and ce are synchronous with respect to the clock and need valid set-up and hold times. 2. address is for internal register, not the external bus, i.e., address needs to be qualified by one of the address counter con trol signals. notes: 1. ce 0 = v il , ce 1 = v ih . 2. for reading port, oe is a don't care on the collision detection logic. please refer to truth table iv for specific cases. 3. leading port output flag might output 3t cyc 2 + t cols after address match. 4. address is for internal register, not the external bus, i.e., address needs to be qualified by one of the address counter con trol signals.
6.42 idt70t3339/19/99s preliminary high-speed 2.5v 512/256/128k x 18 dual-port static ram industrial and commercial tempe rature ranges 22 timing waveform of sleep mode (1,2) ( 4 ) ( 3 ) notes: 1. ce 1 = v ih. 2. all timing is same for left and right ports. 3. ce 0 has to be deactivated ( ce 0 = v ih ) three cycles prior to asserting zz (zzx = v ih ) and held for two cycles after asserting zz (zzx = v ih ). 4. ce 0 has to be deactivated ( ce 0 = v ih ) two cycles prior to de-asserting zz (zzx = v il ) and held for three cycles after de-asserting zz (zzx = v il ).
6.42 idt70t3339/19/99s preliminary high-speed 2.5v 512/256/128k x 18 dual-port static ram industrial and commercial temp erature ranges 23 functional description the idt70t3339/19/99 provides a true synchronous dual-port static ram interface. registered inputs provide minimal set-up and hold times on address, data, and all critical control inputs. all internal registers are clocked on the rising edge of the clock signal, however, the self-timed internal write pulse width is independent of the cycle time. an asynchronous output enable is provided to ease asyn- chronous bus interfacing. counter enable inputs are also provided to stall the operation of the address counters for fast interleaved memory applications. a high on ce 0 or a low on ce 1 for one clock cycle will power down the internal circuitry to reduce static power consumption. multiple chip enables allow easier banking of multiple idt70t3339/19/99s for depth expansion configurations. two cycles are required with ce 0 low and ce 1 high to re-activate the outputs. interrupts if the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. the left port interrupt flag ( int l ) is asserted when the right port writes to memory location 7fffe (hex), where a write is defined as ce r = r/ w r = v il per the truth table. the left port clears the interrupt through access of address location 7fffe when ce l = v il and r/ w l = v ih . likewise, the right port interrupt flag ( int r ) is asserted when the left port writes to memory location 7ffff (hex) and to clear the interrupt flag ( int r ), the right port must read the memory location 7ffff (3ffff or 3fffe for idt70t3319 and 1ffff or 1fffe for idt70t3399). the message (18 bits) at 7fffe or 7ffff (3ffff or 3fffe for idt70t3319 and 1ffff or 1fffe for idt70t3399) is user-defined since it is an addressable sram location. if the interrupt function is not used, address locations 7fffe and 7ffff (3ffff or 3fffe for idt70t3319 and 1ffff or 1fffe for idt70t3399) are not used as mail boxes, but as part of the random access memory. refer to truth table iii for the interrupt operation. collision detection sleep mode the idt70t3339/19/99 is equipped with an optional sleep or low power mode on both ports. the sleep mode pin on both ports is asynchronous and active high. during normal operation, the zz pin is pulled low. when zz is pulled high, the port will enter sleep mode where it will meet lowest possible power conditions. the sleep mode timing diagram shows the modes of operation: normal operation, no read/write allowed and sleep mode. for normal operation all inputs must meet setup and hold times prior to sleep and after recovering from sleep. clocks must also meet cycle high and low times during these periods. three cycles prior to asserting zz (zzx = v ih ) and three cycles after de-asserting zz (zzx = v il ), new reads or writes are not allowed. if a write or read operation occurs during these periods, the memory array may be corrupted. validity of data out from the ram cannot be guaranteed immediately after zz is asserted (prior to being in sleep). during sleep mode the ram automatically deselects itself. the ram disconnects its internal clock buffer. the external clock may continue to run without impacting the rams sleep current (i zz ). all outputs will remain in high-z state while in sleep mode. all inputs are allowed to toggle. the ram will not be selected and will not perform any reads or writes. collision is defined as an overlap in access between the two ports resulting in the potential for either reading or writing incorrect data to a specific address. for the specific cases: (a) both ports reading - no data is corrupted, lost, or incorrectly output, so no collision flag is output on either port. (b) one port writing, the other port reading - the end result of the write will still be valid. however, the reading port might capture data that is in a state of transition and hence the reading port?s collision flag is output. (c) both ports writing - there is a risk that the two ports will interfere with each other, and the data stored in memory will not be a valid write from either port (it may essentially be a random combination of the two). therefore, the collision flag is output on both ports. please refer to truth table iv for all of the above cases. the alert flag ( col x ) is asserted on the 2nd or 3rd rising clock edge of the affected port following the collision, and remains low for one cycle. please refer to collision detectiontiming table on page 21. during that next cycle, the internal arbitration is engaged in resetting the alert flag (this avoids a specific requirement on the part of the user to reset the alert flag). if two collisions occur on subsequent clock cycles, the second collision may not generate the appropriate alert collision detection on the idt70t3339/19/99 represents a significant advance in functionality over current sync multi-ports, which have no such capability. in addition to this functionality the idt70t3339/19/99 sustains the key features of bandwidth and flexibility. the collision detection function is very useful in the case of bursting data, or a string of accesses made to sequential addresses, in that it indicates a problem within the burst, giving the user the option of either repeating the burst or continuing to watch the alert flag to see whether the number of collisions increases above an acceptable threshold value. offering this function on chip also allows users to reduce their need for arbitration circuits, typically done in cpld?s or fpga?s. this reduces board space and design complexity, and gives the user more flexibility in developing a solution. flag. a third collision will generate the alert flag as appropriate. in the event that a user initiates a burst access on both ports with the same starting address on both ports and one or both ports writing during each access (i.e., imposes a long string of collisions on contiguous clock cycles), the alert flag will be asserted and cleared every other cycle. please refer to the collision detection timing waveform on page 21.
6.42 idt70t3339/19/99s preliminary high-speed 2.5v 512/256/128k x 18 dual-port static ram industrial and commercial tempe rature ranges 24 depth and width expansion the idt70t3339/19/99 features dual chip enables (refer to truth table i) in order to facilitate rapid and simple depth expansion with no requirements for external logic. figure 4 illustrates how to control the various chip enables in order to expand two devices in depth. the idt70t3339/19/99 can also be used in applications requiring expanded width, as indicated in figure 4. through combining the control signals, the devices can be grouped as necessary to accommodate applications needing 36-bits or wider. note: 1. a 19 is for idt70t3339, a 18 is for idt70t3319, a 17 is for idt70t3399. 5652 drw 22 idt70t3339/19/99 ce 0 ce 1 ce 1 ce 0 ce 0 ce 1 ce 1 ce 0 v dd v dd idt70t3339/19/99 idt70t3339/19/99 idt70t3339/19/99 control inputs control inputs control inputs control inputs ub , lb , r/ w , oe , clk, ads , repeat , cnten a 19 /a 18/ a 17 (1) figure 4. depth and width expansion with idt70t3339/19/99
6.42 idt70t3339/19/99s preliminary high-speed 2.5v 512/256/128k x 18 dual-port static ram industrial and commercial temp erature ranges 25 jtag ac electrical characteristics (1,2,3,4) jtag timing specifications notes: 1. guaranteed by design. 2. 30pf loading on external output signals. 3. refer to ac electrical test conditions stated earlier in this document. 4. jtag operations occur at one speed (10mhz). the base device may run at any speed specified in this datasheet. tck device inputs (1) / tdi/tms device outputs (2) / tdo trst t jcd t jdc t jrst t js t jh t jcyc t jrsr t jf t jcl t jr t jch 5652 drw 23 , notes: 1. device inputs = all device inputs except tdi, tms, and trst. 2. device outputs = all device outputs except tdo. 70t3339/19/99 symbol parameter min. max. units t jcyc jtag clock input period 100 ____ ns t jch jtag clock high 40 ____ ns t jcl jtag clock low 40 ____ ns t jr jtag clock rise time ____ 3 (1) ns t jf jtag clock fall time ____ 3 (1) ns t jrst jtag reset 50 ____ ns t jrsr jtag reset recovery 50 ____ ns t jcd jtag data output ____ 25 ns t jdc jtag data output hold 0 ____ ns t js jtag setup 15 ____ ns t jh jtag hold 15 ____ ns 5652 tbl 15
6.42 idt70t3339/19/99s preliminary high-speed 2.5v 512/256/128k x 18 dual-port static ram industrial and commercial tempe rature ranges 26 identification register definitions system interface parameters notes: 1. device outputs = all device outputs except tdo. 2. device inputs = all device inputs except tdi, tms, and trst . 3. the boundary scan descriptive language (bsdl) file for this device is available on the idt website (www.idt.com), or by conta cting your local idt sales representative. note: 1. device id for idt70t3319 is 0x334. device id for idt70t3399 is 0x335. instruction field value description revision number (31:28) 0x0 reserved for version number idt device id (27:12) 0x333 (1) defines idt part number idt jedec id (11:1) 0x33 allows unique identification of device vendor as idt id register indicator bit (bit 0) 1 indicates the presence of an id register 5652 tbl 16 scan register sizes register name bit size instruc tio n (ir) 4 bypass (byr) 1 identification (idr) 32 boundary scan (bsr) note (3) 5652 tbl 17 instruction code description extest 0000 forces contents of the boundary scan cells onto the device outputs (1) . places the boundary scan register (bsr) between tdi and tdo. bypass 1111 places the bypass register (byr) between tdi and tdo. idcode 0010 loads the id register (idr) with the vendor id code and places the register between tdi and tdo. highz 0100 places the bypass register (byr) between tdi and tdo. forces all device output drivers to a high-z state except col x & int x outputs. clamp 0011 uses byr. forces contents of the boundary scan cells onto the device outputs. places the bypass register (byr) between tdi and tdo. sample/preload 0001 places the boundary scan register (bsr) between tdi and tdo. sample allows data from device inputs (2) to be captured in the boundary scan cells and shifted serially through tdo. preload allows data to be input serially into the boundary scan cells via the tdi. reserved 0101, 0111, 1000, 1001, 1010, 1011, 1100 several combinations are reserved. do not use codes other than those identified above. p rivate 0110, 1110, 1101 fo r inte rnal us e o nly. 5652 tbl 18
6.42 idt70t3339/19/99s preliminary high-speed 2.5v 512/256/128k x 18 dual-port static ram industrial and commercial temp erature ranges 27 ordering information notes: 1. 166mhz i-temp is not available in the bf-208 package. 2. 200mhz is not available in the bf-208 and dd-144 packages. corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-5166 831-754-4613 santa clara, ca 95054 fax: 408-492-8674 dualporthelp@idt.com www.idt.com the idt logo is a registered trademark of integrated device technology, inc. a power 999 speed a package a process/ temperature range blank i commercial (0c to +70c) industrial (-40c to +85c) bc dd bf 256-pin bga (bc-256) 144-pin tqfp (dd-144) 208-pin fpbga (bf-208) 200 166 133 5652 drw 24 70t3339 70t3319 70t3399 9mbit (512k x 18-bit) synchronous dual-port ram 4mbit (256k x 18-bit) synchronous dual-port ram 2mbit (128k x 18-bit) synchronous dual-port ram s xxxxx device type idt speed in megahertz standard power , commercial only (2) commercial & industrial (1) commercial & industrial preliminary datasheet: definition "preliminary' datasheets contain descriptions for products that are in early release. idt clock solution for idt70t3339/19/99 dual-port idt dual-port part number dual-port i/o specitications clock specifications idt pll clock device idt non-pll clock device voltage i/o input capacitance input duty cycle requirement maximum frequency jitter to l e r a n c e 70t3339/19/99 2.5 lvttl 8pf 40% 200 75ps 5t2010 5t9010 5t905, 5t9050 5t907, 5t9070 5652 tbl 19
6.42 idt70t3339/19/99s preliminary high-speed 2.5v 512/256/128k x 18 dual-port static ram industrial and commercial tempe rature ranges 28 datasheet document history: 01/20/03: initial datasheet 04/25/03: page 11 added capacitance derating drawing page 12 changed t ins and t inr specs in ac electrical characteristics table 11/11/03: page 10 updated power numbers in dc electrical characteristics table page 12 added t ofs symbol and parameter to ac electrical characteristics table page 21 updated collision timing waveform page 22 added collision detection timing table and footnotes page 26 updated highz function in system interface parameters table page 27 added idt clock solution table

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